1. Field of the Invention
The present invention relates to a lateral semiconductor device, particularly for use in integrated circuits.
2. Description of the Related Art
The present invention relates generally to high voltage lateral semiconductor devices manufactured by the use of an insulating substrate and is generally concerned with the distribution of the electric field in such devices. The insulating substrate consists of a dielectric material with a given permittivity εin, and may be made of sapphire, diamond or other dielectric material. Alternatively the substrate may be formed by a combination of different materials (with different permittivities), such as silicon dioxide, nitride, aluminium nitride and the like. The dielectric material may also be air, as used in membrane technology as previously described in our WO-A-02/25700 and US-A-2002-0041003, the entire contents of which are hereby incorporated by reference. The semiconductor material placed above the dielectric substrate, into which the lateral device is formed, is commonly made of silicon. This type of structure is referred here as SOD (Semiconductor-on-Dielectric)
As shown schematically in FIG. 1, a typical lateral high-voltage diode 1 (which forms part of a semiconductor device such as Lateral MOSFET) fabricated using the SOD technology has a basic configuration of a p+ region 2 and an n+ region 3 at opposite ends separated by a central n drift region 4 of lower conductivity, all of which are formed in a semiconductor layer 5 which is formed on a dielectric layer 6. The p+ and n+ regions 2,3 are more highly doped than the n drift region 4. In the blocking/off-state mode of the diode, a high voltage reverse bias is applied to a terminal (not shown) connected to the n+ region 3 with respect to the terminal (not shown) placed on the p+ region 2. As the reverse bias is increased, a depletion layer develops across the p+/n junction 2/4. The bulk of the depletion layer forms within the n region 4 so that a significant portion of the applied reverse bias is sustained inside the n region 4.
During the blocking mode of operation, the voltage also develops in the insulating substrate 6. A schematic map of the potential lines is given in FIG. 2.
The diode 1 breaks down when the electric field within the semiconductor reaches the critical electric field in silicon, initiating avalanche of mobile carriers. The breakdown voltage can then be calculated approximately as the area under the electric field taken on a line AB at the surface of the device. The breakdown occurs commonly at the surface of the device. FIG. 3 shows a typical electric field distribution at the surface of the device when the device experiences breakdown. The insulating substrate plays an important role in the breakdown capability of the device. In particular, we found that the permittivity of the insulating substrate affects the electric field distribution at the surface of the semiconductor layer.
Ideally the n drift region 4 is completely depleted of carriers when a high reverse bias is applied between the diode terminals and the electric field is distributed uniformly at the surface of the device. In reality, due to a two-dimensional effect of the potential line distribution, in SOD structures there are two electric field peaks developing at the surface of the device, at the p+/n and n+/n junctions respectively. We have found that the lower the dielectric permittivity of the insulating substrate, the lower the electric field peaks in the semiconductor and hence the higher the breakdown voltage. We have also found that the electric field peaks are in fact dependent on the ratio between the electric permittivity of the semiconductor layer and that of the substrate. The higher this ratio, the lower the values of the electric field peaks at the p+/n and n+/n junctions resulting in higher breakdown voltage. While the argument was given here for an n drift region which is more lowly doped that the n+ and p+ regions, the same applies for a p type lowly doped drift region.
FIG. 4 shows the electric field distribution at the surface for two different dielectric permittivities of the substrate when the same reverse bias voltage is applied across the two terminals placed above the regions n+ and p+ 2,3. The permittivity of the semiconductor layer placed above the dielectric layer is the same in each case. It can be seen that the dielectric permittivity of the substrate affects strongly the electric field distribution at the surface of the semiconductor and that the lower the permittivity of the substrate with respect to that of the semiconductor, the more advantageous the lateral electric field distribution in the device in terms of the SOD structure breakdown.
To demonstrate that this effect is purely two dimensional and depends on the ratio between the permittivities and not the absolute values of the permittivities of the two layers one can consider the simpler situation where two dielectric layers are placed above each other and two electrodes are placed at the surface of the device on top of the first dielectric as shown in FIG. 5. If the two layers have different permittivities but the ratio is the same, the electric field distribution at the surface remains unchanged when the same voltage is applied across the two electrodes. FIG. 6(a) shows the distribution of the electric field in this case. If the ratio of the permittivities between the top layer and the bottom layer is higher, the peaks of the electric field at the surface are reduced as shown in FIG. 6(b). If the opposite is assumed (i.e. the ratio between the permittivity of the top layer and the bottom layer is lower), the peaks of the electric field in the vicinity of the electrodes are higher.
The SOD analysis is more complex than the example described above since it involves a semiconductor junction and a depletion region extending from the p+/n junction into the drift layer, but the physical concept is similar. FIG. 5 shows a cross-section of a semiconductor diode with a dielectric layer (oxide) and a dielectric substrate placed below; the breakdown voltage is a function of the permittivity of the dielectric substrate and the electric field distribution at the surface of the diode. The breakdown characteristics and the electric field distribution are obtained through advanced numerical simulations using standard semiconductor software. It can be seen from the electric field distribution that the lower the permittivity of the insulating substrate (e.g. εr=1 for air) with respect to that of the semiconductor layer above (e.g. εr=11.9 for silicon), the higher the voltage supported by the middle part of the drift region, thus releasing the “pressure” on the edges of the drift region in the vicinity of the p+/n and n+/n junctions. The numerical simulations of the diode breakdown shown in FIG. 5 also indicate that the breakdown is considerably affected by the dielectric substrate permittivity relative to the permittivity of the semiconductor layer.
It can be inferred from the analysis above that the lower the dielectric permittivity of the insulating (dielectric) substrate with respect to the semiconductor permittivity, the higher the breakdown ability of the SOD structure. In this respect the membrane technology which has air (with a relative permittivity of one) as the dielectric substrate is most advantageous. If a combination of dielectric materials is used in the substrate, it is advantageous that the permittivity of those materials be low. The thickness of the substrate also affects the surface distribution of the electric field and the higher this thickness the higher the breakdown voltage. However, above a certain thickness the effect is no longer visible. If a combination of dielectric materials is used, it is more advantageous that the material with lower permittivity be thicker than that with higher permittivity. For example if a membrane type structure is used for a high voltage lateral device as described in our WO-A-02/25700 and US-A-2002-0041003. Where a silicon dioxide layer is placed between the air and the semiconductor (which layer may be used as an etch-stop to form the membrane), it would be advantageous in terms of the breakdown ability that this layer be as thin as possible to reduce the electric field peaks at the surface of the semiconductor. This is because the silicon dioxide has a relative permittivity higher than that of the air.
The analysis above has assumed that the n drift region 4 shown in FIG. 1 is completely depleted of carriers during the off-state. This means that the doping of the drift region should be low. However, if the diode structure is used in a switching device such as a LDMOSFET, the low doping of the n drift region will result in an undesirable high on-state resistance. To break this trade-off, F. Udrea et al describe in “3D RESURF Double-Gate MOSFET: A revolutionary power device concept”, Electronic Letters, vol.34, no.8, April 1998, a structure that allows the doping of the drift region 4 to be high while the structure is still depleted during the blocking-mode in the off-state. The prior art structure described in this paper is shown in FIG. 7. The 3D-RESURF concept is based on alternate n and p stripes with relatively higher doping than those used in standard diodes and their width significantly smaller than their length. When the reverse voltage is applied across the main terminals, the structure depletes first across the n/p stripes well before depletion of the n and p drift regions could occur caused by the electric field developed across the n+/p and p+/n junctions. This allows the doping of the drift layer to be raised above the level given by the one-dimensional condition of full depletion along the p+/n/n+ diode.
The structure was proposed on a SOI substrate, which generally has a silicon layer placed on a buried oxide, which in turn is placed on a semiconductor substrate. The structure is also applicable to SOD but the effect of the dielectric substrate is not discussed in the above cited paper.
In the paper “Lateral Unbalanced SuperJunction for high breakdown voltage on SOI” in Proceedings of 2001 International Symposium on Power Semiconductor Devices and ICs (ISPSD'01), p.395-398, June 2001 by R. Ng, F. Udrea et al, there is disclosed a 3D RESURF structure on an SOI substrate (the SOI substrate being formed by a semiconductor material which is separated from the active semiconductor layer through a buried insulating layer) based on alternate n/p drift regions which has a considerable excess of ion charge in the n drift region compared to that in the p drift region in order compensate for the negative charge in the inversion/accumulation layer formed under the buried oxide in the semiconductor substrate. This paper refers strictly to the situation of a semiconductor layer placed under a buried insulating layer. The excess of the charge in the n drift region compared to the p drift region is solely for the purpose of compensating the negative mobile charge in the inversion/accumulation layer (which is formed at the surface of the semiconductor substrate) underneath the buried insulating layer, thus achieving an overall compensation of charge in the structure, which leads to a higher breakdown voltage. This mobile charge is formed of electrons and is the result of a Metal-Oxide-Semiconductor effect when a high reverse voltage is applied to the high voltage terminal. Since in the SOD structure, which is used in the preferred embodiment of the present invention, there is no semiconductor substrate placed below the high voltage terminal, there is no mobile charge (mobile electrons) formed under the semiconductor layer below the high voltage terminal and therefore there is no need to have an overall increase in the charge of the n drift region compared to that of the p drift region.
These references do not discuss the contribution of a dielectric substrate placed under the semiconductor layer and hence do not propose any means of reducing the peaks at the two ends of the drift region caused by the non-zero dielectric permittivity of the substrate.